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代做COMPSCI 4043 System and Networks 2020代写数据结构语言

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System and Networks (IT)

COMPSCI 4043

Thursday 21 May 2020

Answer ALL 3 Questions

This examination paper is worth a total of 60 marks

1.    (a)     Express the following in 16-bit two’s complement code, giving your answers in hexadecimal. Show your working.

i.       180                    ii.       -30                                   [4]

(b)    Give the range of values that can be represented by a 32-bit two’scomplement code (express the range using powers of 2) and explain why. [2]

(c)     Find two 8-bit codewords, X and Y, such that X+Y overflows if the code being used is unsigned but  does not if it is two’s complement. Now find two codewords, W and Z, such that W+Z overflows in both codes. Explain your reasoning carefully. [4]

(d)    Write a Sigma16 program that takes an n-element array, X, of unsigned numbers and subtracts 1

from each element, except when the element is already 0. Assume that nisan unsigned variable in data memory indicating the number of elements in the array. Fully comment your code. [7]

(e)    Referring to your solution for (d), discuss what maximum value of n it would work for, explaining what factors you are considering. [3]

For reference, here is part of the instruction set of the Sigma16 CPU.

lea

Rd, x[Ra]

Rd:= x +Ra

load

Rd, x[Ra]

Rd:= mem[x +Ra]

store

Rd, x[Ra]

mem[x +Ra]:=Rd

add

Rd,Ra,Rb

Rd:= Ra+Rb

sub

Rd,Ra,Rb

Rd:= Ra-Rb

mul

Rd,Ra,Rb

Rd:= Ra*Rb

div

Rd,Ra,Rb

Rd:= Ra/Rb,  R15:=Ra mod Rb

and

Rd,Ra,Rb

Rd:= Ra AND Rb

inv

Rd,Ra,Rb

Rd:= NOT Ra

or

Rd,Ra,Rb

Rd:= Ra OR Rb

xor

Rd,Ra,Rb

Rd:= Ra XOR Rb

cmplt

Rd,Ra,Rb

Rd:= Ra

cmpeq

Rd,Ra,Rb

Rd:= Ra=Rb

cmpgt

Rd,Ra,Rb

Rd:= Ra>Rb

shiftl

Rd,Ra,Rb

Rd:=Ra logic shifted left Rb places

shiftr

Rd,Ra,Rb

Rd:=Ra logic shifted right Rb places

jumpf

Rd, x[Ra]

If Rd=0 then PC:=x+Ra

jumpt

Rd, x[Ra]

If Rd<>0 then PC:=x+Ra

jal

Rd, x[Ra]

Rd:= pc, pc: =x +Ra

trap

Rd,Ra,Rb

PC:= interrupt handler

jump

x[Ra]

PC:= x +Ra

2      (a)      Distinguish between primary and secondary memory and explain briefly how the CPU accesses data

stored in each. If auser were experiencing problems with the performance of a PC running a modern operating system using virtual memory, under what circumstances would you recommend increasing the amount of primary memory? Explain your reasoning. [6]

(b)     The following Sigma 16 code is intended to take an 8-element array (only first element is shown) and add all the elements placing the result in another variable, sum. However, although the code will assemble, it contains several errors.

i.       Draw up a register-use table for the program (suitable for inclusion as comment).

ii.       Identify the errors, in each case explain what is wrong, and how you would correct it.

iii.       Write out the corrected program.

LEA R1,1[R0] ;Set R1 to constant 1

ADD R2,R0,R0 ;i:=0

LEA R3,n[R0] ;Set R3 to n

ADD R4,R0,R0 ;sum=0

FORLOOP CMPEQ R5,R2,R3 ;Is i

JUMPF R5,OUT[R0] ;if yes, exit

LOAD R6,X[R0] ;load x[i]

ADD R4,R4,R1 ;sum:=sum + x[i]

ADD R1,R2,R2 ;i:=i+1

JUMP FORLOOP[R0] ;loop

OUT STORE R4,sum[R0]

TRAP R0,R0,R0

; Data Area

n DATA 8

sum DATA 0

x DATA 0                                                                 [6]

(c)      Estimate how many cycles the corrected program would take to run. [4]

(d)     In the corrected program estimate the advantage a system with a cache memory would gain if a primary memory cycle takes 10ns and a cache cycle 1ns. [4]

3.          (a)           In Internet communications, what is the function of an IP packet and how does the internetwork get such a packet to its intended destination. [6]

(b)          An IP interface has the address 10.100.20.6. What binary value does this address represent? Also write the value in hex. Show your working. [3]

(c)           A network interface is implemented as a memory-mapped Input/output device. What does this mean and what characteristics would a memory-mapped network interface require? [5]

(d)          When new data arrives at such an interface, the device interrupts the CPU. Explain why and how

this happens and, when it does, how the CPU will react. In your answer refer to the notion of an interrupt handler routine and say what, if you were to program such a routine, you would have it do (only a high-level informal description is required, not code). [6]


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