EEC 210
HW 8
1. An amplifier has a low-frequency forward gain of 5000 and its transfer function has three negative real poles with magnitudes 300 kHz, 2 MHz, and 25 MHz.
a. Calculate the dominant-pole magnitude required to give unity-gain compen- sation of this amplifier with a 45° phase margin if the original amplifier poles remain fixed. What is the resulting bandwidth of the circuit with the feed- back applied?
b. Repeat (a) for compensation in a feedback loop with a closed-loop gain of 20 dB and 45° phase margin.
2. The amplifier in the previous problem is to be compensated by reducing the magni- tude of the most dominant pole.
a. Calculate the dominant-pole magnitude required for unity-gain compensation with 45° phase margin. Also, calculate the corresponding bandwidth of the circuit with the feedback applied. Assume that the remaining poles do not move.
b. Repeat (a) for compensation in a feedback loop with a closed-loop gain of 20 dB and 45° phase margin.
3. For the CMOS operational amplifier shown below, calculate the open-loop voltage gain, unity-gain bandwidth, and slew rate. Assume that the gate of M9 is con- nected to the positive power supply and that the W/L of M9 has been chosen to cancel the right-half-plane zero. Also, assume that Xd = 0. 1 µm for all transistors operating in the active region, and use Table 2.4 at the end of this homework for other parameters. Compare your results with a SPICE simulation.
4. Assume the circuit below is used to generate the bias voltage to be applied to the gate of M9 in the op amp in the previous problem. Calculate the W/L of M9 required to move the right half-plane zero to infinity. Use L = 1 µm for all transis- tors. Let W8 = W10 = 150 µm, and W11 = W12 = 100 µm. Assume that Xd = 0. 1 µm for all transistors operating in the active region, and use Table 2.4 at the end of this homework for other parameters.
5. Consider the op amp in Problem 3 and the bias circuit in Problem 4. Assuming that the zero has been moved to infinity, determine the maximum load capacitance that can be attached directly to the output of the op amp and still maintain a phase margin of 45° . Neglect all higher order poles except any due to the load capaci- tance. Use the value of W/L obtained in Problem 4 for M9 with the bias circuit shown in that problem.