CEG 2136
LAB 2
Design, Simulation and Experimental Verification of Sequential Logic Circuits
1. Purpose:
This lab will enable students gain practice in the conversion of functional requirements into logic circuits and their implementation using the Altera DE2-115 board.
The purpose of this lab is to introduce students to the design of sequential circuits based on Altera’s Quartus development environment and their implementation and testing with an FPGA.
• Enter the design of synchronous counters using Quartus II graphics editor
• Assign the input-output pins and prepare the design for downloading and testing on the Altera DE2-115 board
• Test the counter:
- Display the counter outputs as binary values on LEDs and 7-segment displays.
- Using an oscilloscope to trace and record the waveforms at various flip-flops.
2. Requirements of the Lab:
Each group is required to submit a report over the Brightspace. The recommendation is that the structure of your report will be compatible with the indications given in the “Lab General Instructions” posted in the section Laboratories/Intro of your BS. However, the following need to be included in your report:
* The log of what you did
* The screen shots of all schematics and all waveform. diagrams
* Compilation, simulation and downloading messages (if any)
* Your test results
3. Equipment and Supplies:
* Quartus II (web edition)
* Altera DE2-115 board with
- USB-Blaster cable
- Power supply 12V/2A
* Oscilloscope Keysight/Agilent MSOX2012A (2 analog + 8 digital channels)
* Probe
* Coaxial cable
* Wires
* Ribbon cable
4. References:
i. Chapter1 and 2 of the Textbook: Computer Systems Architecture, Morris Mano, 3rd Ed
ii. DE2-115 User Manual posted in the Documentation section under the Laboratories tab of CEG2136 Virtual Campus.
5. Logic Design of Counters
5.1. For each of the following counters (a. and b.):
• Draw the state diagram and derive the excitation table for all the flip-flops involved in the counter (the excitation table for counter a. is already given below),
• Derive and simplify the Boolean expression of every flip-flop input using K maps.
a. 3 bit synchronous modulo 6 counter
The block diagram in Fig. 1.(a) has to observe the counting sequence given in Figure 1(b) This counter counts as long as its control input count is active high. The counter activates the rollover RO output during the state before returning to 0. The circuit is to be implemented with JK flip flops which have active-low asynchronous Reset inputs (CLRN); the flip-flops’ clock inputs (CLK) are connected all together to CCLK (counter clock).
count Q2 Q1 Q0 RO
CCLK Reset
|
Figure 1 : (a) Block diagram and
(b) State Diagram of a Modulo 6 counter
Table 1 : The Excitation Table for the JK flip-flops Modulo 6 counter
Use K-maps to derive the minimized excitation equations (i.e., the Synchronous Inputs of Q2 , Q1 , Q0) and the counter output RO.
b. 4-bit synchronous BCD counter (BQ3, BQ2, BQ1 , BQ0) observes the following counting sequence and it counts as long as its control input count is active high.
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001
↑ ← ← ← ← ← ← ← ← ← ← ← ← ← ← ← ← ← ← ← ← ← ← ← ← ← ← ↓
5.2. Devise a modulo 60 counter (mod60) by cascading the two counter modules designed above at 5.1a and 5.1b as shown below
BRO BQ3 BQ2 BQ1 BQ0 count CCLK BCD
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Figure 2: Block diagram of Modulo 60 counter
PART I - Schematic capture and logic circuits simulation
To capture your design in the Altera’s development environment you can use Quartus’ “New Project Wizard”, or you can proceed manually with the following design flow. The following steps refer to the mod6 counter, but the procedure is scalable to other counters. For the modulo 6 and BCD counters designed above execute the following:
1. Using the logic equations derived above, draw the circuit diagrams using the graphics editor of Quartus in a schematic file and save it as the corresponding .bdf file. You can use the JK Flip-Flop with Enable input (jkffe) from Quartus storage Library. The Enable input of jkffe facilitates implementation of counters ’ control input count (Figure 1.a). Equally, you can use jkff and implement your own count control circuit.
You may want to include I/O pins, as well. Use the counter’s signal names suggested in the block diagram (Figure 1.a) when editing the names of the pins of your circuit. In the Project Navigator pane select the Files tab; right-click on your schematic file (.bdf) and select Set as Top Level Entity
Also export the schematics as a jpeg file or print it for inclusion in your report.
2. To assign EP4CE115F29C7 to your project (if you did not do it already) go to Assignments in the main menu, select Device and in the window Device chose Cyclone IV E for the Device Family and then from the list of Available Devices choose EP4CE115F29C7 . Then click OK to close the Device window.
In the main menu select Processing → Start compilation, or click on the toolbar icon ► , or press Ctrl+L.
3. To visualize the input, output and control signals of your counter (clock, reset, flip- flops’ outputs, etc.) during its functional simulation, you have to create a University VWF file where you will catch the time diagram of these signals.
4. To define the set of pins of your test circuit, while in the .vwf tab, do select in the main menu Edit >> Insert >> Insert Node or Bus … and click on Node Finder.
5. In the option Filter of the popped-up Node Finder window choose ‘Pins: All’, then click on the button List, select all found nodes (from the left list) and move all found nodes to the right pane by clicking , then press OK to return to your .vwf files. Now you may want to make sure that you use Quartus IIsimulator: in the Simulation
Waveform. Editor window, under Simulation menu, go to Options and select Quartus II Simulator as the simulator.
6. To set the duration of your experiment (say to 200 ns) you have to setup the End by selecting Edit Set End Time. Then, to set time characteristics of the simulation clock, click on the clock signal (CCLK) to select it, then do Edit >> Value>> (Overwrite) Clock and in the Clock window put a Period of 20 ns (a close approximation of the DE2-115 board clock) and click OK. Make sure you assign logic 1 to Reset by Forcing High (1) - in Edit > Value, to allow your counter to operate under the CCLK control. Also, you may want to assign count = 0 for the first period (at least), and to 1 for the rest of the test, to verify that your counter counts only when count = 1. To do direct time editing of input count:
With the mouse left button, click and drag the mouse from 0ns to 40.0ns for count; this interval would then be highlighted. Go to the waveform. manipulation buttons and select 0 for this interval (click on the toolbar).
Click and drag the mouse from 40 ns to 200 ns for Node D and select 1 for this interval (click on the toolbar).
The binary representation of the counter’s states can be displayed by grouping Q2 - Q0 in a bus; make sure that you have their time waveforms represented from top- down as Q2 Q1 Q0 ; else, left click on a signal and drag it to the right position.
7. To choose a grid of 10 ns, do: Edit >> Grid Size, then put 10 ns for Period.
Run your functional simulation (Processing Start Simulation or click on the toolbar icon ) and inspect the time diagram of your Simulation Report – Simulation Waveforms window and verify if your synchronous counter follows the given counting sequence; if it doesn’t, verify your equations and/or debug your circuit.
NOTE: Again, make sure that under the simulator is the Quartus II simulator. Under Simulation menu, goto Options and select Quartus II Simulator as the simulator.
Show the simulation to your instructor and capture it in a graphic format for your lab report (copy to clipboard all the waveforms and paste them into a .doc file); to get a better visualization of your waveforms, you may want to change the time base in your .vwf file by choosing in Edit/End Time a Time = 0.5 μs) .
At this point you can run a functional simulation. Show the design and demonstrate the simulations to your TA.
8. Return to one of your counter’s .bdf file, such that you can see its schematic in the worksheet of the Graphic Editor, and, from File >> Create/ Update >> Create Symbol Files For Current File, you can create a symbol (.bsf file) for your synchronous counter. Create a symbol for the other counter as well.
9. Use the two counters’ symbols to design a modulo 60 counter (mod60.bdf), based on the schematic presented above in Figure 2 of section 5.2 of 5. Logic Design of Counters, on page 2. Make sure you include I/O pins for all signals that you may want to visualize. Now mod60.bdf should be Set as Top Level Entity and eventually compiled.
PART II (Testing experiments)
Three approaches can be considered to experimentally test the counters designed above.
II-1. Manual control - by deriving CCLK from a push-button of the DE-115 board and displaying the flip-flops’ outputs on LEDs or/and on a 7-segment display as shown below.
II-2. Automatic,free running (highest speed) - by connecting CCLK to the DE2-
115 board general clock (CCLK - generated on board) and visualizing the flip-flops’ outputs and CCLK with an oscilloscope.
II-3. Automatic,free running (low speed) - by deriving the counters clock CCLK from the DE2-115 board general clock (CCLK - generated on board) with the frequency divider provided in the support files (clock1Hz.vhd and clock1Hz.bsf) and displaying the flip-flops’ outputs on LEDs or/and 7- segment displays.
NOTE: While the first two approaches (II-1 and II-2) can be done only in person in the
lab, the last one (II-3) can be performed both in person or remotely / online. However, this term, the lab stations are setup for in-person use only.
II-1. Manual control
For this mode you have to derive the counter’s clock CCLK from a push-button (KEY0) and displaying the flip-flops’ outputs on LEDs as shown below (block diagram of Figure 3).
Figure 3: COUNTER test circuit
Figure 4: Block diagram of push-buttons on DE2-115 board
The DE2-115 board provides four push-button switches as shown in Figure 4. Each of these switches is debounced using a Schmitt Trigger circuit, as indicated in Figure 5. The four outputs called KEY0, KEY1, KEY2, and KEY3 of the Schmitt Trigger devices are connected directly to the Cyclone IV E FPGA’s pins shown in Figure 4. Each push-button switch provides a high logic level when it is pressed, and provides a low logic level when depressed. Since the push-button switches are debounced (Figure 5), they are appropriate for being used as clock or reset inputs in a circuit. [1,32]
You will learn more about switch debouncing in CEG3136 (Computer Architecture II).
Figure 4: Block diagram of 4 push-button on DE2-115 boards
Figure 5: Debouncing mechanism (Schmitt Trigger)
1. Create a .bdf file for a test circuit for any of the modulo 6 or BCD counters with the Quartus graphic editor. Save the file (as test1.bdf) and set the project to the current file with Set as Top Level Entity. The corresponding counter Symbol created above can be inserted into your schematics by going Edit >> Insert Symbol and looking for it in the Project directory of the Symbol Libraries.
Add I/O pins to the inserted symbol into your logic diagram, for the signals specified in Figures 1 and 2: CCLK, count, RO, {Q2, Q1, Q0 - for mod6} and {BQ3, BQ2, BQ 1, BQ0 - for BCD}.
A 7-segment display will be employed to directly display the decimal value of the counter’s state. The least significant digit display will be used for the BCD counter, while the 10’s display will show the contents of the mod6 counter, as indicated below.
Each segment of a display is identified by an index from 0 to 6, with the positions given in Figure 6 below and are driven by a BCD-to-7 segment decoder (7446 – found in Quartus ’ Libraries/others/maxplus2).
Figure 6: 7 segment display for the BCD counter
As indicated in Figure 7 below, the inputs of the BCD-to-7 segment decoder are connected to the counter’s outputs (BCD in this example: BQ3 – BQ0), as the decoder’s outputs (OA, OB, … OG) will drive the 7-segment display. The displays ’ inputs (HEX0[k], k=0,1, … 6) are connected through the PCB to dedicated FPGA’s pins that need to be driven by the 7446, as shown in Figure 6 and specified in Table 3. [1,36]
Figure 7: Seven segment display decoder
Input D is the most significant bit and A bit is least significant. The OA-OG are output lights controls (HEX0[k], k=0,1, … 6) for 7 segment LCD display. Inputs LTN, RBIN and BIN are not required hence will be tied to high (1).
2. Assign the EP4CE115F29C7 device number to your design (Assignments Device) and then assign pin numbers as shown in Tables 2 and 3. This integrated circuit has 528 pins through which the FPGA can be connected to the PCB (Printed Circuit Board) on which it is mounted. Some pins are assigned fixed functions, such as, pin C1 is ground, B1 is Vcc, pin Y2 is clock input, etc. These pins are connected through PCB to different components of the PCB, such as the local power regulator (pins B1, C1) or 50 MHz oscillator and clock generator (pin Y2). The rest of the pins can be programmed to be connected to any logic circuits implemented by the user on FPGA. However, various electronic components on the PCB (such as LED’s, switches, 7-segment displays, etc.) are connected to dedicated pins which must be programmed by the designer who may want to employ these components. For static verification of your counter, the DE-115 board contains all the components needed to implement your test circuit, but they need to be linked to your circuit through the FPGA’s pins. Tables 2 and 3 contain the signals that you need to connect through the pins to LED’s and switches, and which, on their turn, are already hardwired to those pins.
Table 2: Manual Control BCD Pin Assignment [1,35]
Logic circuit signal
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FPGA pin assignment
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Component
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CCLK
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PIN_M23
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KEY0
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BQ3
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PIN_E24
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LEDG3
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BQ2
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PIN_E25
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LEDG2
|
BQ1
|
PIN_E22
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LEDG1
|
BQ0
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PIN_E21
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LEDG0
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RESET
|
PIN_AB28
|
SW0
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The pins assignment for the 14 pins of the two 7-segment displays (Digit 0 being used for the BCD counter and Digit 1 for the mod6 counter) are given in Table 3 below.
Table 3: Pin Assignment of 7-segment displays (shown as BCD/mod6)
3. The pins ’ assignment follows the same procedure like in Lab 1, as shown below:
a. Select Assignments → Assignment Editor; under Category select ALL.
b. Double-click on the entry <<new>> in the column labeled To. Press the binoculars to
open the Node finder window, then select
i. Filter → Pins: all, then click on List.
ii. Select (highlight) CCLK, Q3, Q2, Q1, Q0 and RESET from the left column of Nodes Found and then click on “>” to have all CCLK, Q3, Q2, Q1, Q0 and RESET in the right Selected Nodes column. The content of the left column is entirely copied to the right (without having to select them) by simply hitting “>>” .
iii. Click OK to close the Node Finder window.
c. On the box to the right of the new CCLK entry, in the column labeled Assignment Name, double click the blank field and select Location (Accept wildcards/groups) from the drop-down list (speedup advancing in this list by writing “L”) and then hit Enter on your keyboard. Note: once Location (Accept wildcards/groups) is selected, text defaults to Location.
d. In the Value column for the CCLK entry type PIN_M23, as indicated in Table 2.
e. Repeat steps c and d to assign the rest of the signals to the pins as described by Tables 2 and 3
NOTE: refer to the DE2-115 User Manual for the number of the FPGA’spins to which the 7-segment display’s inputs are connected [1,36].
NOTE: Alternatively, instead of the Assignment Editor, you can use the Pin Planner, from Assignments → Pins.
4. Compile your project with the assigned pins.
5. Make sure the RUN/PROG switch (SW19; leftmost toggle switch) is set to RUN
6. Select Tools → Programmer in the Quartus II window. From Hardware Settings, in the Currently Selected Hardware box, select USB-Blaster and click Close.
NOTE: if the USB-Blaster doesn’t show-up in the list of Currently Selected
Hardware, close the window and open it again. You might have to repeat this process a few times.
7. In the Programmer window, check that the *.sof file is listed. If it is not then click the Add File button on the left panel and look for the *.sof file under the …/output_files directory in the current working directory.
8. Make sure Program/Configure is checked-in. Click Start and verify your circuit. Remember that a LED illuminates when its control input is 1.
NOTE: Once done you do not need to save the *.cdf file.
9. Find experimentally the count table of your synchronous counter by pressing the KEY0 pushbutton until you rollover a full counting sequence. Verify that the output of your synchronous counter matches the corresponding state diagram you were initially given.
10. Demonstrate the operation of your circuit to your instructor.